June 02, 2020

Design and Implementation of High Speed ​​Communication Interface of FPGA+DSP

Abstract: In the fields of radar signal processing and digital image processing, the real-time performance of signal processing is very important. Due to the advantages of FPGA chip processing in the underlying algorithm of large data volume and the advantages of DSP chip in complex algorithm processing, the application of DSP+FPGA real-time signal processing system is more and more extensive. ADI's TIgerSHARC family of DSP chips has superior floating-point processing performance, and DSP's DSP+FPGA processing system is widely used in complex signal processing applications. At the same time, in this kind of real-time processing system, real-time communication of data between FPGA and DSP chip is very important.

There are two main ways for TIgerSHARC series DSP chips to communicate with the outside: bus mode and link port mode. The link port mode is more suitable for real-time communication between the FPGA and the DSP. With the increasing amount of real-time signal processing operations, multi-DSP parallel processing is widely adopted. They share the bus to map memory space to each other. If the FPGA is connected to the bus, it will inevitably lead to competition between the FPGA and the DSP bus. At the same time, the bus mode is used to communicate with the FPGA. The address and data line pins of the DSP are many, and the I/O pin resources of the FPGA are too much. The use of link port communication can not only effectively alleviate the pressure on the DSP bus, but also has a fast transmission speed and a relatively small connection between the FPGA and the FPGA. Therefore, the link port mode is more suitable for real-time data between the FPGA and the DSP. Communication.

1 Link port analysis and comparison of TS101 and TS201

Both TS101 and TS210 are high-performance floating-point processing chips, both of which are currently widely used in complex signal processing applications. TS201 is a new chip introduced after TS101. The core clock can reach up to 600MHz, and its performance is relatively better than TS101. The link port of TS201 uses low-voltage differential signal LVDS technology, which consumes less power and has more anti-noise performance. it is good. Table 1 shows a detailed comparison of the performance of the two chip link ports, where the TS101 core clock operates at 250 MHz and the TS201 core clock operates at 500 MHz.

Since the TS101 transceivers share one channel, only half-duplex communication can be realized. The TS201 makes the transceiver end into two independent channels, which can realize full-duplex communication. In theory, the data transmission rate can be doubled. Although the TS201's link port transceiver channel is independent, in fact, the two transceiver mechanisms are basically the same, both rely on the transceiver buffer and shift register to send and receive data. However, the link port design inside the FPGA does not have to be limited to this, as long as the link port communication protocol is met and communication is reached.

2 FPGA and DSP link port communication

2.1 Link Port Communication Protocol Analysis

The link port of TS101 has 11 pins, which pass through 8 data lines (LxDAT[7..0], where x can be 0, 1, 2 or 3, which represents the link number 0-3 of TS101 or TS201. One, the following is the same for data transmission, and uses three control lines (LxCLKOUT, LxCLKIN, LxDIR) to control the data transmission clock, communication grip and data transmission direction. LxDIR is an output pin that informs the link port that the current working state is received or sent, and can be left unused. The TS201 has a total of 24 pins on the link port, receiving and transmitting 12 pins, and transmitting data through the LVDS data line (LxDAT_P/N[3..0]) and the clock line (LxCLK_P/N). LxACK and LxBCMP# ('#' stands for signal low active) are used to inform the reception ready and the end of the data block transmission.

The key to using FPGA and DSP to communicate through the link port is to make the handshake signal of the two parties reach agreement and promote the data transmission. In fact, if the LVDS signal form of TS201 has been converted, the data format transmitted by the TS101 and TS201 link ports is the same, both are DDR data triggered by the double edge of the clock, and the number of data transmitted each time is An integer multiple of 4 long words (ie 128 bits). In view of the commonality of the data of the above two types of chip link ports, when the FPGA is used to communicate with the two types of chips, the design of the data buffer portion of the receiving and transmitting should be very similar, but the design of the communication handshake signal portion should be separately considered. The following is given separately.

2.2 FPGA-based TS101 link port design

Figure 1 shows the design of FPCA and TS101 for half-duplex link port communication (both LxCLKOUT and LxCLKIN are described in terms of FPCA). The interface consists of three parts: receive, control and transmit. The FPGA clock of this design is 40MHz, the TS101 core clock is set at 250MHz, the link port clock is set to the DSP core clock of 8 frequency division, and the actual data transmission rate of FPGA and DSP is 62.5MBps.

(1) Receiving part: It consists of two parts: encoding and buffering. Since the number of errors in the link port is in the form of DDR, it is inconvenient to buffer the data. In this paper, the altddio module in the Quartus II MegafuncTIons is used to separate the rising edge data from the falling edge data. Note that the falling edge data output of this module will lag the rising edge data by 1 clock cycle. The output should use the link port clock signal (LxCLKIN) to align the data through the D flip-flop. The inclock of the module must use the link port clock signal to ensure the correct reading of the data, as shown in Figure 2. Since the DSP internal data is a 32-bit long word, a set of D flip-flops should be used to 32-bit the data before writing to the receive buffer. Note that the DSP link port first transmits the lower 8 bits of the 32-bit data.

(2) Control part: It consists of the token conversion module and the control module, which is the core part of the whole design, completes the control of each part and communicates with the internal of the FPGA (through a set of CTL signals). The link communication handshake of TS101 is completed by two clock signal verification token commands, that is, when the transmitter drives the high LxCLKOUT signal to be low, it is sent as a token request to the receiver. If the receiving end is ready to receive, the receiving end drives LxCLKIN high; if the LxCLKIN signal is still high after the token is issued for 6 clock cycles, the shoulder data transmission (the above clock signals are all analyzed by the transmitting end view). In this design, the token conversion module is responsible for verifying the token and sending the token. It should be noted here that since the clock signal (PLL_32ns) used to verify the low number of tokens is obtained by multiplying the FPGA clock signal (CLK) by the phase-locked loop, it is asynchronous with the DSP link port clock, so when verifying the token When the counter counts 5 low levels, it can be considered that the communication handshake has been reached, otherwise data may be lost. After the handshake is reached, the control module is notified to output a control signal to the receive or transmit buffer, wherein the receive control signal includes a write cache clock and a write enable. The transmit control signals include a read buffer clock, a read enable, and a DSP interrupt signal (DSP_IRQ), wherein the write buffer clock is obtained by dividing the link port clock, and the read buffer clock is obtained by the phase locked loop multiplier FPGA operating clock.

(3) Sending part: similar to the receiving part, it is also composed of two parts: south coding and cache. The corresponding design is basically the same, so I will not introduce too much here. Since the minimum unit of the number of data transmitted by the DSP link port is 4 32-bit words, that is, 8 link clock cycles, the clock corridor should be sent every 8 clock cycles to make up 128 bits to avoid transmission errors. The redundant data DSP can be discarded by itself. The transmitting part uses the DSP external interrupt mode instead of the link port interrupt mode to notify the DSP to receive data.

The link port communication protocol of TS101 requires the link port receiver to pull LxCLKOUT low after one cycle of transmission start. If it can continue to receive, it will be pulled high in the next cycle as a connection test. In actual operation, it is found that when the FPGA receives data, the LxCLKOUT signal can be driven high all the time, and the data can be correctly received without special connection test. In addition, when the link port data is sent, since the 8-bit data to be transmitted is already matched in the transmission buffer, the PLL_16ns signal obtained by multiplying the FPGA clock signal (CLK) can be used to read the transmission buffer, and the read data is The link port sends data, and then divides the falling edge of the PLL_16ns signal to obtain the transmission clock signal of the link port.

Due to space limitations, this paper only gives the timing diagram of FPCA receiving TS101 data, as shown in Figure 3. LxCLKIN, LxDAT[7..0] are the link port output clock and data of the DSP, and LxCLKOUT is the feedback ready signal of the FPGA. In the simulation, the link port data adopts 32 8-bit data of 1F-3E (hexadecimal), that is, 8 32-bit data from 2222201F to 3E3D3C3B; the PLL_32ns signal is generated by the internal phase-locked loop of the FPGA and is asynchronous with the DSP link port clock. The 32ns clock signal is used to verify the token instruction; the W_FIFO_EN signal is sufficient to write the buffer enable signal, and the receive buffer is enabled when the token is verified; the DSP_DAT signal is the 32-bit data transmitted by the DSP through the link gate, and passes through the link port. The data is encoded; the W_BUF_CLK signal is obtained by dividing the link port clock, and the 32-bit DSP data corresponding to the rising edge is written into the receive buffer to complete the receiving process.

2.3 FPGA-based TS201 link port design

Figure 4 shows the block diagram of the FPGA and TS201 for link port communication. Since the handshake signal of the TS201 is large, the design of the link port of the TS101 is easier. The FPGA clock of this design is 50MHz, the TS101 core clock is 500MHz, the link port clock is divided by 4 of the DSP core clock, and the 4-bit mode is adopted. The one-way actual data transmission rate is 125MBps.

The link port data and clock of the TS201 adopt LVDS signals, which have the advantages of high speed, low power consumption and low noise. Cyclone series chips not only support LVDS signals, but also integrate LVDS conversion modules, which provides great convenience for design. It should be noted that the PCB traces of the two poles of the LVDS signal should be matched during hardware design, and attention should be paid to the matching of the resistor network.

The link port of TS201 has two transmission modes: 1bit and 4bit. This article uses 4bit as an example to design. The signals given in Figure 4 are all LVDS converted signals. Since the TS201 transceiver is made up of two separate channels, the design of the FPGA should be designed as two channels accordingly, truly full-duplex communication, and the transmission and reception do not affect each other. The receiving and transmitting part is basically the same as the design of the TS101, and the transmitting part also uses the external interrupt mode to notify the DSP to receive the link port data. The communication handshake signal of TS201 has ACK and BCMP# signals. The ACK signal is used to notify the reception that it is ready. In real-time signal processing, the data transmission is generally not allowed to wait, so this signal is ready. The BCMP# signal is used to inform the end of the data block transfer. When the number of DMA transfer data can be determined, this pin can be left floating.

The transmission and reception mechanism of the TS201 link port is very similar. This paper only gives the timing diagram of the transmission data, as shown in Figure 5. L1_IRQ is an external interrupt sent by the FPGA to the DSP to notify the DSP to receive data; L1_ACKI is the DSP ready receive signal; R_BUF_EN is the read transmit buffer enable signal; the link port clock L1_CLKOUT is the read buffer clock R_CLK falling edge of the second The frequency division is performed corresponding to the 4-bit link port data L1_DA-To read from the buffer. Note that there is a nanosecond delay in the read buffer and clock division.

3 DSP's corresponding settings

The link ports of TS101 and TS201 are configured with two registers, a control register (LCTLX) and a state register (LSTATx). LCTLx is used to control the transmission of the link port, and LSTATx is used to notify the working state of the link port. The TS101 link port clock frequency can be 8, 4, 3 or 2 divided by the core clock. By setting the SPD bit in the LCTLx, this design will set the SPD position to 000, which is the core clock divided by 8. Since the receiving and transmitting channels of the TS201 are independent, their control registers are divided into a receiving control register (LRCTLx) and a transmission control register (LTCTLx). The TS101 link port transmit clock frequency can be the same as the core clock or divided by 4, 2, and 1.5, by setting the SPD bit in the LTCTLx. In this paper, the SPD position is set to 100, which is the core clock divided by 4, and the LRCTLx/LTCTLx (connected to the TDSIZE bit is set to 4 bit transmission mode. If the BCMP# signal is left floating, be sure to set the LRCTLx RBCMPE bit to 0.

There are two ways to start the DSP's link port DMA transfer: use link interrupts and utilize the DSP's four external interrupts (IRQ0-IRQ3). Both interrupt modes require the DMA TCB register to be configured in the interrupt service routine to initiate the receive DMA channel of the link port. Since the priority of the external interrupt is higher than the link port interrupt, data loss can be avoided. The communication method designed in this paper notifies the DSP to receive data in the external interrupt mode. In the DMA TCB register configuration process, in order to ensure that the program is not interrupted by other interrupts, all other interrupts can be masked at the beginning of the interrupt service routine, and the masked interrupt bits are restored before the interrupt service routine returns.

In this paper, the link ports of two typical DSP chips of TIgerSHARC series are analyzed and compared, and the specific method of link port multiplication between FPGA and these two DSP chips is given. The design of the DSP link port is implemented in the FPGA, and the specific setting method of the DSP for link port communication is given. Since the retransmission of data in real-time processing will seriously affect the real-time processing, the link port communication design of this paper does not verify the transmitted data. The FPGA-based intersection design given in this paper has strong versatility and can be applied to various application systems based on TS101/TS201 to improve the communication capability inside the system. It can also be used for data transmission between boards and improve the external system. Communication ability.

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